View 4H2259_8414024.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ka i - 18000 image sensor 4320 (h) x 4144 (v) interline ccd im age sensor june 4 , 201 4 device performance s pecification revision 3 .0 ps 0067
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 2 table of contents summary specification ................................ ................................ ................................ ................................ ................................ ......................... 5 description ................................ ................................ ................................ ................................ ................................ ................................ .... 5 features ................................ ................................ ................................ ................................ ................................ ................................ ......... 5 applications ................................ ................................ ................................ ................................ ................................ ................................ .. 5 ordering information ................................ ................................ ................................ ................................ ................................ ............................ 6 device description ................................ ................................ ................................ ................................ ................................ ................................ . 7 architectu re ................................ ................................ ................................ ................................ ................................ ................................ .. 7 pixel ................................ ................................ ................................ ................................ ................................ ................................ ................. 9 quadrant boundaries ................................ ................................ ................................ ................................ ................................ .............. 10 vertical to horizontal transfer ................................ ................................ ................................ ................................ ............................. 11 horizontal register to floating diffusion ................................ ................................ ................................ ................................ .......... 12 output ................................ ................................ ................................ ................................ ................................ ................................ ......... 13 output spice model ................................ ................................ ................................ ................................ ................................ ................. 14 esd protection ................................ ................................ ................................ ................................ ................................ .......................... 15 bond pads (left half) ................................ ................................ ................................ ................................ ................................ ................ 16 bond p ads (right half) ................................ ................................ ................................ ................................ ................................ .............. 17 bond pad design ................................ ................................ ................................ ................................ ................................ ....................... 18 bond pad locations ................................ ................................ ................................ ................................ ................................ ................. 19 die orientation ................................ ................................ ................................ ................................ ................................ ......................... 21 pad one mark ................................ ................................ ................................ ................................ ................................ ............................ 22 die alignment mark ................................ ................................ ................................ ................................ ................................ ................. 22 performance ................................ ................................ ................................ ................................ ................................ ................................ ............ 23 power C estimated ................................ ................................ ................................ ................................ ................................ ................... 23 imaging pe rformance ................................ ................................ ................................ ................................ ................................ .......................... 24 image performance operational conditions ................................ ................................ ................................ ................................ ..... 24 imaging performance specifications ................................ ................................ ................................ ................................ ................... 24 typical performance curves ................................ ................................ ................................ ................................ ................................ .. 25 quantum efficiency ................................ ................................ ................................ ................................ ................................ ............. 25 angular quantum efficiency ................................ ................................ ................................ ................................ .............................. 25 horizontal and vertical mtf ................................ ................................ ................................ ................................ .............................. 26 defect definitions ................................ ................................ ................................ ................................ ................................ ................................ 27 specifications ................................ ................................ ................................ ................................ ................................ ............................. 27 operation ................................ ................................ ................................ ................................ ................................ ................................ .................. 28 maximum ratings ................................ ................................ ................................ ................................ ................................ ..................... 28 maximum voltage ratings between pin (or function) ................................ ................................ ................................ ................... 28 expected range of dc bias operating conditions ................................ ................................ ................................ .......................... 28 ac operating conditions ................................ ................................ ................................ ................................ ................................ ........ 29 expected range of clock levels ................................ ................................ ................................ ................................ ....................... 29 power up sequence ................................ ................................ ................................ ................................ ................................ ............. 30 clock line capacitances ................................ ................................ ................................ ................................ ................................ ...... 31 timi ng requirements (for 17 mhz operation) ................................ ................................ ................................ ................................ . 34 timing ................................ ................................ ................................ ................................ ................................ ................................ .......... 35 image readout flow ................................ ................................ ................................ ................................ ................................ ............ 35 electronic shutter timing flow ................................ ................................ ................................ ................................ ......................... 36 electronic shutter description ................................ ................................ ................................ ................................ .......................... 37 large signal output ................................ ................................ ................................ ................................ ................................ ............. 37 line timing ................................ ................................ ................................ ................................ ................................ ............................. 38
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 3 edge alignment v1 and v2 clock ................................ ................................ ................................ ................................ ...................... 39 frame timing ................................ ................................ ................................ ................................ ................................ ......................... 40 pixel timing ................................ ................................ ................................ ................................ ................................ ............................ 41 video loading ................................ ................................ ................................ ................................ ................................ ....................... 45 noise factors ................................ ................................ ................................ ................................ ................................ ................................ .......... 46 storage and handling ................................ ................................ ................................ ................................ ................................ .......................... 47 storage conditions ................................ ................................ ................................ ................................ ................................ ................... 47 esd ................................ ................................ ................................ ................................ ................................ ................................ ............... 47 cover glass care and cleanliness ................................ ................................ ................................ ................................ ......................... 47 environmental exposure ................................ ................................ ................................ ................................ ................................ ........ 47 mechanical drawings ................................ ................................ ................................ ................................ ................................ ........................... 48 complete d assembly ................................ ................................ ................................ ................................ ................................ ............... 48 quality assurance and reliability ................................ ................................ ................................ ................................ ................................ .. 50 quality and reliability ................................ ................................ ................................ ................................ ................................ ............. 50 repl acement ................................ ................................ ................................ ................................ ................................ .............................. 50 liability of the supplier ................................ ................................ ................................ ................................ ................................ ........... 50 liability of the customer ................................ ................................ ................................ ................................ ................................ ........ 50 test data retention ................................ ................................ ................................ ................................ ................................ ................. 50 mechanic al ................................ ................................ ................................ ................................ ................................ ................................ .. 50 life support applications policy ................................ ................................ ................................ ................................ ................................ .... 50 revision changes ................................ ................................ ................................ ................................ ................................ ................................ ... 51 mtd/ps - 1416 ................................ ................................ ................................ ................................ ................................ ............................. 51 ps0067 ................................ ................................ ................................ ................................ ................................ ................................ ......... 51
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 4 table of figures figure 1: sensor architecture ................................ ................................ ................................ ................................ ................................ ...... 7 figure 2: sensor architecture ................................ ................................ ................................ ................................ ................................ ...... 8 figure 3: pixel architecture, top and side view ................................ ................................ ................................ ................................ ..... 9 figure 4: 4 - quadrant intersection pixels ................................ ................................ ................................ ................................ ................ 10 figure 5: vertical to horizontal transfer architecture ................................ ................................ ................................ ....................... 11 figure 6: horizontal register to floating diffusion architecture ................................ ................................ ................................ .... 12 figure 7: output architecture ................................ ................................ ................................ ................................ ................................ ... 13 figure 8: esd protection ................................ ................................ ................................ ................................ ................................ ............. 15 figure 9: bond pad schematic (left half) ................................ ................................ ................................ ................................ ................. 16 figure 10: bond pad schematic (right half) ................................ ................................ ................................ ................................ ............ 17 figure 11: bond pad design ................................ ................................ ................................ ................................ ................................ ....... 18 figure 12: bond pad assignment table ................................ ................................ ................................ ................................ .................. 20 figure 13: die orientation ................................ ................................ ................................ ................................ ................................ .......... 21 figure 14: pad one marker ................................ ................................ ................................ ................................ ................................ ......... 22 figure 15: die alignment marks ................................ ................................ ................................ ................................ ................................ 22 figure 16: monochrome quantum efficiency ................................ ................................ ................................ ................................ ........ 25 figure 17: angular quantum efficiency ................................ ................................ ................................ ................................ .................. 25 figure 18: kai - 18000 horizontal mtf ................................ ................................ ................................ ................................ ...................... 26 figure 19: kai - 18000 vertical mtf ................................ ................................ ................................ ................................ ........................... 26 figure 20: power up and power down sequence ................................ ................................ ................................ ................................ 30 figure 21: vccd clock negative overshoot ................................ ................................ ................................ ................................ ............ 30 figure 22: external diode protection recommendation ................................ ................................ ................................ ..................... 30 figure 23: clock line capacitance ................................ ................................ ................................ ................................ ............................ 31 figure 24: reset clock line capacitance ................................ ................................ ................................ ................................ ................ 32 figure 25: rd and og line capacitances ................................ ................................ ................................ ................................ ................ 33 figure 26: image readout flow ................................ ................................ ................................ ................................ ................................ . 35 figure 27: electronic shutter timing flow ................................ ................................ ................................ ................................ ............. 36 figure 28: line timing ................................ ................................ ................................ ................................ ................................ ................. 38 figure 29: line timing detail ................................ ................................ ................................ ................................ ................................ ..... 38 figure 30: example of vertical clock crossover - targeted at 50% ................................ ................................ ................................ . 39 figure 31: frame timing ................................ ................................ ................................ ................................ ................................ ............. 40 figure 32: pixel timing ................................ ................................ ................................ ................................ ................................ ................ 41 figure 33: reset and hccd timing detail ................................ ................................ ................................ ................................ .............. 42 figure 34: reset clock waveform ................................ ................................ ................................ ................................ ............................ 43 figure 35: electronic shutter timing ................................ ................................ ................................ ................................ ....................... 44 figure 36: video output waveform ................................ ................................ ................................ ................................ ......................... 45 figure 37: completed assembly ................................ ................................ ................................ ................................ ............................... 48 figure 38: glass drawing ................................ ................................ ................................ ................................ ................................ ............. 49
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 5 summary specification kai - 18000 image sensor d escription the kai - 18000 image sensor is a high - performa nce 18 - million pixel sensor designed for 30 frames/sec video applications. the 8.0 m square pixels with microlenses provide high sensitivity and the large full well capacity results in high dynamic range. the forty outputs and with binning capabilities al low for 30 frames per second (fps) progressive scan video images at a pixel rate of 17 mhz. the vertical overflow drain structure provides antiblooming protection and enables electronic shuttering for precise exposure control. other features include low da rk current, negligible lag and low smear. f eatures ? 30 frames per second ? 17 mhz data rate ? progressive scan a pplications ? customer restricted parameter typical value architecture interline ccd; progressive scan total number of pixels 4320 (h) x 4224 (v) = approx. 18.2 m number of effective pixels 4320 (h) x 4144 (v) = approx. 17.9 m number of active pixels 4320 (h) x 4160 (v) = approx. 18.0 m number of outputs 40 pixel size 8.0 m (h) x 8.0 m (v) imager size 47.89 mm (diagonal) chip size 37.00 mm (h) x 36.00 mm (v) aspect ratio 1:1 saturation signal 50,000 e - peak quantum efficiency (qe) 55% solar weighted average qe 400 to 900 nm 31% output sensitivity 30 v/e - total sensor noise (at 17 mh z ) <25 e - vccd capacity 60,000 e - dark current at 20 c < 0.5 na/cm 2 dark current doubling temperature 7 c dynamic range 60 db charge transfer efficiency > 0.99999 blooming suppression 200x smear - 85 db image lag <10 e - maximum data rate 20 mhz all parameters above are specified at t = 20 c
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 6 ordering information catalog number product name description 4h 2259 kai - 18000 - aaa - xr - a e - cust proprietary pkg - rad monochrome, pga package, taped clear cover glass with ar coating (both sides), rad 4h0 260 kai - 18000 - aba - xr - a e - cust proprietary pkg - em monochrome, microlens, pga package, taped clear cover glass with ar coating (both sides), em 4h0 261 kai - 18000 - aba - xr - a m - cust proprietary pkg - mech monochrome, microlens, pga package, taped clear cover glass with ar coating (both sides), mech sample 4h0402 kai - 18000 - aba - xr - aa - cust proprietary pkg - fm monochrome, microlens, pga package, taped clear cover glass with ar coating (both sides), fm see application note product naming conven tion for a full description of the naming convention used for image sensors. for reference documentation, including information on evaluation kits, please visit our w eb site at www.truesenseimaging.com . please address all inquiries and purchase orders to: truesense imaging, inc. 1964 lake avenue rochester, new york 14615 phone: (585) 784 - 5500 e - mail: info@truesenseimaging.com on semiconductor reserves the right to change any information contained herein without notice. all information furnished by on se miconductor is believed to be accurate.
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 7 device description a rchitecture figure 1 : sensor architecture to allow for 30 fps video with a 17 mhz pixel rate, there must be 40 outputs. there are twenty outputs across the top and twenty outputs across the bottom of the image sensor. the vertical ccd (vccd) is split in half. the pixel design in the top half is an exact mirror image of the bottom half pixel design. the horizontal ccd (hccd) on each half is split into 20 blocks, each 216 columns wide. the end of each block turns within the space of one column towards an output amplifier. there are six dummy hccd pixels between the output amplifier and the imaging array. after each vccd clock cycle one line will be transferred into each hccd block. once the hccd clocks are started after the vccd line transfer, the first six clock cycles will transfer empty charge packets to the output amplifier. those are then followed by 216 clock cycles containing valid image data. there is no dead sp ace between each hccd block. there also are no dark columns on the image sensor. dark columns are not possible on a hccd with more than two outputs. 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 8 figure 2 : sensor architecture the clock inputs of k ai - 18000 are separated into four quadrants. there is no dead space between each quadrant. the wiring is such that if some portion of the image sensor fails, the clock drivers and biases for that quadrant may be powered down while the other quadrants still image. each quadrant has 32 dark rows adjacent to the hccd. the dark rows are pixels where the transfer gate between the photodiode and vccd is permanently turned off. these dark rows will only contain vccd dark current and image smear signal. they will n ot contain photodiode dark current. in between the dark rows and imaging pixels are 8 photoactive buffer rows. the buffer rows are a zone to account for larger than normal manufacturing variations in micro - lens formation near the edges of the imaging area. there are buffer columns on the left and right sides of the image sensor. the buffer columns do not transfer into any hccd so they will not appear at any output amplifier. 2160 x 2072 quadrant a 2160 x 2072 quadrant b 2160 x 2072 quadrant d 2160 x 2072 quadrant c 8 buffer rows 32 dark rows 8 buffer rows 32 dark rows v1a v2a vha v1b v2b vhb 8 buffer rows 32 dark rows 8 buffer rows 32 dark rows v1d v2d vhd v1c v2c vhc h1d1 h2d1 h1d2 h2d2 h1c1 h2c1 h1c2 h2c2 h1a1 h2a1 h1a2 h2a2 h1b1 h2b1 h1b2 h2b2 resetd resetc reseta resetb oga, rda ogb, rdb ogc, rdc ogd, rdd
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 9 p ixel figure 3 : pixel architecture, top and side view an electronic representation of an image is formed when incident photons falling on the sensor plane create electron - hole pairs within the individual silicon photodiodes. these photoelectrons are collected locally by the formation of potential wells at eac h photosite. below photodiode saturation, the number of photoelectrons collected at each pixel is linearly dependent upon light level and exposure time. when the photodiodes charge capacity is reached, excess electrons overflow into the substrate to preve nt blooming. charge is transferred from the photodiodes to the vccd when the v2 gate is pulsed above +9v. the pixel array layout of the imager is symmetrically mirrored about the middle center seam. the pixel operation is the same for pixels in the top an d the bottom of the array. t r a n s f e r g a t e v 1 v 2 p h o t o d i o d e c h a r g e t r a n s f e r v 1 v 2 p h o t o d i o d e c h a r g e t r a n s f e r v c c d t o p h a l f b o t t o m h a l f p h o t o d i o d e v c c d v c c d p h o t o d i o d e l i g h t s h i e l d
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 10 q uadrant b oundaries figure 4 : 4 - quadrant intersection pixels the design requirement for kai - 18000 was to allow for a quadrant to be de - activated should something go wrong with that quadrant. this requi rement for independent quadrant clock signals necessitates an electrical break in the poly silicon gates along a vertical boundary between the a/b and c/d quadrants. the light shield is used to carry the v1 and v2 clock voltages from the perimeter of the s ensor to the center poly silicon gates. thus, an electrical break in the light shield at the a/d and b/c quadrant boundaries is required. these electrical breaks will affect the photo - response of the pixels bordering the quadrant boundaries. the quantum ef ficiency is expected to be different by 10 to 20% relative to the rest of the pixel array.
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 11 v ertical to h orizontal t ransfer figure 5 : vertical to horizontal transfer architecture when the v1 and v2 timing inputs are clocked, charge in every pixel of the vccd is shifted one row towards the hccd. the last row of gates next to the hccd has a separate clock line, vh. the timing requirements to meet 30 frames/sec mandate a very short horizontal retrace time which is insufficient to allow a complete vccd transfer across the entire pixel array. to allow enough time for vccd charge transfer the v1 and v2 clocks are operated during hccd read out. this extends the v1 and v2 charge transfer times out to the length of one line time. to pre vent charge from the vccd from transferring into the hccd during hccd readout the last gate, vh, is clocked separately. vh is normally held low to block transfer from the vccd to the hccd. when an entire line has be en read out of the hccd and v1 is low and v2 is high, then vh is rapidly clocked from low to high and back low again in less than 1 s. the short pulse on vh transfers the next row into the hccd. h1 must be high and h2 must be low during the vh transfer time from the vccd to the hccd. v 1 v 2 c h a r g e t r a n s f e r v 1 v h c h a r g e t r a n s f e r c h a r g e t r a n s f e r h 1 h 2 h 1 h 2
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 12 h orizontal r egister to f loating d iffusion figure 6 : horizontal register to floating diffusion architecture the hccd for each output block has a total of 222 pixels. 216 of those pixels receive valid image data directly from the vccd. the remaining 6 pixels are between the floating diffusion and the first valid image pixel. the dummy pixels are required to provide space for wiring connections and the amplifier. charge is transferred across og to the floating diffusion on the falling edge of h2. the reset gate should be pulsed on the rising edge of h2. v 1 v 2 c h a r g e t r a n s f e r v 1 v h c h a r g e t r a n s f e r c h a r g e t r a n s f e r h 2 h 1 _ b 1 h 2 _ b 1 o g r e s e t 6 d u m m y p i x e l s t o a m p l i f i e r r e s e t d r a i n h 1 _ b 2 h 1 _ b 2 h 1 _ b 2 h 1 _ b 2 h 2 _ b 2 h 2 _ b 2 h 2 _ b 2 h 2 _ b 2
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 13 o utput figure 7 : output architecture charge packets contained in the horizontal register are dumped pixel by pixel onto the floating diffusion (fd) output node wh ose potential varies linearly with the quantity of charge in each packet. the amount of potential change is determined by the expression ? vfd= ? q/cfd. a three - stage source - follower amplifier is used to buffer this signal voltage off chip with slightly less than unity gain. the translation from the charge domain to the voltage domain is quantified by the output sensitivity or charge to voltage conversion in terms of microvolts per electron ( v/e - ). after the signal has been sampled off chip, the reset clock ( r) removes the charge from the floating diffusion and resets the fd potential to the reset drain voltage (rd). when the image sensor is operated in the binned or summed modes there may be more than 50,000 electrons in the output signal. the image sensor is designed with a 30 v/e charge to voltage conversion on the output. this means a full signal of 50,000 electrons will produce a 1500 mv change on the output amplifier. the output amplifier was designed to handle an output swing of 1500 mv at a pixel r ate of 17 mhz. the output amplifier will not be able to swing more than 1500 mv in the binned or summed interlaced modes. the hccd will also not hold more than 65,000 electrons. if signal clipping or blooming of the hccd is to be avoided the photodiode charge capacity should be reduced below 50,000 electrons by increasing the substrate voltage. f l o a t i n g d i f f u s i o n h c c d c h a r g e t r a n s f e r s o u r c e f o l l o w e r # 1 s o u r c e f o l l o w e r # 2 s o u r c e f o l l o w e r # 3 r d r o g h 2 h 2 h 1 h 2 h 1 v d d v o u t h 1
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 14 o utput s pice m odel these spice model parameters are measured values for dc conditions. all transistor model parameters are for nmos transistors spice level 1. the video output bond pad has an estimated capacitance of 3pf. load transistors drive transistors 1st stage 2nd stage 1st stage 2nd stage 3rd stage vto - 2.3 - 2.3 - 2.74 - 2.74 - 2.74 lambda 0.0179 0.0179 0.0672 0.0672 0.0672 gamma 0.96 0.96 0.68 0.68 0.68 kp 2.51e - 05 2.51e - 05 2.84e - 05 2.84e - 05 2.84e - 05 phi 0.34 0.34 0.09 0.09 0.09 w (m) 13 96 4.6 37 352 l (m) 5 5 2 2 2 at 17 mhz, the video output bandwidth will be determined entirely by the 3rd stage drive transistor loading. the complete behavior of the kai - 18000 image sensor cannot be fully and accurately modeled with a spice model. rather, these parameters can be used to help estimate the imagers performance along with actual data from the test and characterization system.
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 15 esd p rotect ion figure 8 : esd protection the esd protection circuitry for kai - 18000 is shown in figure 8 . it is mandatory that the pin voltages conform always to this range: esd < pin voltage < esd + 15. there are no exceptions. only reset, og, gnd, h1 and h2 pins are connected to esd circui t. any power up, power down or other transient pulses, even less than 1 nsec pulse width, can cause the circuitry to latch up. in addition, please refer to the specific bond pad locations of esd protection stated in figure 12 : bond pad assignment table . please note that schottky diode d1 is an externally mounted component which the system designer may choose to include. refer to the section on power up sequence for more details .
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 16 b ond p ads ( left half ) figure 9 : bond pad schematic (left half) all pins with identical labels are connected internally on the image sensor. those pins must be wired together externally. all gnd pins are connected internally on the image sensor. the vdd pins are independent to each output. an individual output amplifier may be deactivated by setting vd d to zero volts and disabling the output load current sink. each quadrant has two independent hccd clock inputs. the inputs, v1, v2, vh, og, rd, and reset are all separated by quadrant. 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 gnd vout21 vdd21 gnd vout22 vdd22 gnd vout23 vdd23 gnd vout24 vdd24 gnd vout25 vdd25 h1_d2 h2_d2 gnd vout26 vdd26 reset_d gnd vout27 vdd27 gnd vout28 vdd28 gnd vout29 vdd29 gnd vout30 vdd30 h1_c1 h2_c1 159 rd_d 160 og_d 161 h2_d1 162 h1_d1 163 vh_d 164 v1_d quadrant d 165 v1_d 166 v2_d 167 v2_d 168 esd 169 sub 170 sub 171 gnd 172 v2_a 173 v2_a quadrant a 174 v1_a 175 v1_a 176 vh_a 177 h1_a1 178 h2_a1 179 og_a 180 rd_a gnd vout1 vdd1 gnd vout2 vdd2 gnd vout3 vdd3 gnd vout4 vdd4 gnd vout5 vdd5 h1_a2 h2_a2 gnd vout6 vdd6 reset_a gnd vout7 vdd7 gnd vout8 vdd8 gnd vout9 vdd9 gnd vout10 vdd10 h1_b1 h2_b1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 17 b ond p ads ( right half ) figure 10 : bond pad schematic (right half) 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 gnd vout31 vdd31 gnd vout32 vdd32 gnd vout33 vdd33 gnd vout34 vdd34 reset_c gnd vout35 vdd35 h1_c2 h2_c2 gnd vout36 vdd36 gnd vout37 vdd37 gnd vout38 vdd38 gnd vout39 vdd39 gnd vout40 vdd40 rd_c 90 og_c 89 n/c 88 n/c 87 vh_c 86 quadrant c v1_c 85 v1_c 84 v2_c 83 v2_c 82 esd 81 sub 80 sub 79 gnd 78 v2_b 77 quadrant b v2_b 76 v1_b 75 v1_b 74 vh_b 73 n/c 72 n/c 71 og_b 70 rd_b 69 gnd vout11 vdd11 gnd vout12 vdd12 gnd vout13 vdd13 gnd vout14 vdd14 reset_b gnd vout15 vdd15 h1_b2 h2_b2 gnd vout16 vdd16 gnd vout17 vdd17 gnd vout18 vdd18 gnd vout19 vdd19 gnd vout20 vdd20 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 18 b ond p ad d esign figure 11 : bond pad design each bond pad is 300 m square with 4 wire bond / wafer probe sites. the four sites are delineate d by a 2 m gap in a poly silicon layer underneath the metal pad. it will appear in a microscope as a shallow trench in the metal layer. a metal triangle is located at the center of each side of the bond pad. each bond pad has an esd protection transistor located nearby. not all bond pads will have an esd protection transistor connected. the pads with esd protection are listed in the pad location list i n figure 12 : bond pad assignment table . wire bond / probe site 150 m esd protection bipolar transistor wire bond / probe site wire bond / probe site wire bond / probe site 1 5 0 m
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 19 b ond p ad l ocation s pad pad name function esd x (m) y (m) pad pad name function esd x (m) y (m) 1 gnd gnd yes - 17062 - 17240 158 gnd gnd yes - 17062 17240 2 vout1 vout no - 16482 - 17240 157 vout21 vout no - 16482 17240 3 vdd1 vdd no - 15902 - 17240 156 vdd21 vdd no - 15902 17240 4 gnd gnd yes - 15334 - 17240 155 gnd gnd yes - 15334 17240 5 vout2 vout no - 14754 - 17240 154 vout22 vout no - 14754 17240 6 vdd2 vdd no - 14174 - 17240 153 vdd22 vdd no - 14174 17240 7 gnd gnd yes - 13606 - 17240 152 gnd gnd yes - 13606 17240 8 vout3 vout no - 13026 - 17240 151 vout23 vout no - 13026 17240 9 vdd3 vdd no - 12446 - 17240 150 vdd23 vdd no - 12446 17240 10 gnd gnd yes - 11878 - 17240 149 gnd gnd yes - 11878 17240 11 vout4 vout no - 11298 - 17240 148 vout24 vout no - 11298 17240 12 vdd4 vdd no - 10718 - 17240 147 vdd24 vdd no - 10718 17240 13 gnd gnd yes - 10200 - 17240 146 gnd gnd yes - 10200 17240 14 vout5 vout no - 9860 - 17240 145 vout25 vout no - 9860 17240 15 vdd5 vdd no - 9520 - 17240 144 vdd25 vdd no - 9520 17240 16 h1_a2 h1 yes - 9180 - 17240 143 h1_d2 h1 yes - 9180 17240 17 h2_a2 h2 yes - 8840 - 17240 142 h2_d2 h2 yes - 8840 17240 18 gnd gnd yes - 8391 - 17240 141 gnd gnd yes - 8391 17240 19 vout6 vout no - 7991 - 17240 140 vout26 vout no - 7991 17240 20 vdd6 vdd no - 7591 - 17240 139 vdd26 vdd no - 7591 17240 21 reset_a r yes - 7191 - 17240 138 reset_d r yes - 7191 17240 22 gnd gnd yes - 6694 - 17240 137 gnd gnd yes - 6694 17240 23 vout7 vout no - 6114 - 17240 136 vout27 vout no - 6114 17240 24 vdd7 vdd no - 5534 - 17240 135 vdd27 vdd no - 5534 17240 25 gnd gnd yes - 4966 - 17240 134 gnd gnd yes - 4966 17240 26 vout8 vout no - 4386 - 17240 133 vout28 vout no - 4386 17240 27 vdd8 vdd no - 3806 - 17240 132 vdd28 vdd no - 3806 17240 28 gnd gnd yes - 3238 - 17240 131 gnd gnd yes - 3238 17240 29 vout9 vout no - 2658 - 17240 130 vout29 vout no - 2658 17240 30 vdd9 vdd no - 2078 - 17240 129 vdd29 vdd no - 2078 17240 31 gnd gnd yes - 1560 - 17240 128 gnd gnd yes - 1560 17240 32 vout10 vout no - 1220 - 17240 127 vout30 vout no - 1220 17240 33 vdd10 vdd no - 880 - 17240 126 vdd30 vdd no - 880 17240 34 h1_b1 h1 yes - 540 - 17240 125 h1_c1 h1 yes - 540 17240 35 h2_b1 h2 yes - 200 - 17240 124 h2_c1 h2 yes - 200 17240 36 gnd gnd yes 218 - 17240 123 gnd gnd yes 218 17240 37 vout11 vout no 798 - 17240 122 vout31 vout no 798 17240 38 vdd11 vdd no 1378 - 17240 121 vdd31 vdd no 1378 17240 39 gnd gnd yes 1946 - 17240 120 gnd gnd yes 1946 17240 40 vout12 vout no 2526 - 17240 119 vout32 vout no 2526 17240 41 vdd12 vdd no 3106 - 17240 118 vdd32 vdd no 3106 17240 42 gnd gnd yes 3674 - 17240 117 gnd gnd yes 3674 17240 43 vout13 vout no 4254 - 17240 116 vout33 vout no 4254 17240 44 vdd13 vdd no 4834 - 17240 115 vdd33 vdd no 4834 17240 45 gnd gnd yes 5433 - 17240 114 gnd gnd yes 5433 17240
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 20 pad pad name function esd x (m) y (m) pad pad name function esd x (m) y (m) 46 vout14 vout no 5833 - 17240 113 vout34 vout no 5833 17240 47 vdd14 vdd no 6233 - 17240 112 vdd34 vdd no 6233 17240 48 reset_b r yes 6633 - 17240 111 reset_c r yes 6633 17240 49 gnd gnd yes 7080 - 17240 110 gnd gnd yes 7080 17240 50 vout15 vout no 7420 - 17240 109 vout35 vout no 7420 17240 51 vdd15 vdd no 7760 - 17240 108 vdd35 gnd no 7760 17240 52 h1_b2 h1 yes 8100 - 17240 107 h1_c2 vout yes 8100 17240 53 h2_b2 h2 yes 8440 - 17240 106 h2_c2 vdd yes 8440 17240 54 gnd gnd yes 8858 - 17240 105 gnd gnd yes 8858 17240 55 vout16 vout no 9438 - 17240 104 vout36 vout no 9438 17240 56 vdd16 vdd no 10018 - 17240 103 vdd36 vdd no 10018 17240 57 gnd gnd yes 10586 - 17240 102 gnd gnd yes 10586 17240 58 vout17 vout no 11166 - 17240 101 vout37 vout no 11166 17240 59 vdd17 vdd no 11746 - 17240 100 vdd37 vdd no 11746 17240 60 gnd gnd yes 12314 - 17240 99 gnd gnd yes 12314 17240 61 vout18 vout no 12894 - 17240 98 vout38 vout no 12894 17240 62 vdd18 vdd no 13474 - 17240 97 vdd38 vdd no 13474 17240 63 gnd gnd yes 14042 - 17240 96 gnd gnd yes 14042 17240 64 vout19 vout no 14622 - 17240 95 vout39 vout no 14622 17240 65 vdd19 vdd no 15202 - 17240 94 vdd39 vdd no 15202 17240 66 gnd gnd yes 15770 - 17240 93 gnd gnd yes 15770 17240 67 vout20 vout no 16350 - 17240 92 vout40 vout no 16350 17240 68 vdd20 vdd no 16930 - 17240 91 vdd40 vdd no 16930 17240 69 rd_b rd no 17957 - 17240 159 rd_d rd no - 17960 17240 70 og_b og yes 17957 - 16640 160 og_d og yes - 17960 16640 71 n/c - no 17957 - 16040 161 h2_d1 h2 yes - 17960 16040 72 n/c - no 17957 - 15440 162 h1_d1 h1 yes - 17960 15440 73 vh_b vh no 17957 - 14840 163 vh_d vh no - 17960 14840 74 v1_b v1 no 17957 - 14240 164 v1_d v1 no - 17960 14240 75 v1_b v1 no 17957 - 13640 165 v1_d v1 no - 17960 13640 76 v2_b v2 no 17957 - 13040 166 v2_d v2 no - 17960 13040 77 v2_b v2 no 17957 - 12440 167 v2_d v2 no - 17960 12440 78 gnd gnd yes 17957 - 11840 168 esd esd yes - 17960 11840 79 sub sub no 17808 - 300 169 sub sub no - 17808 300 80 sub sub no 17808 300 170 sub sub no - 17808 - 300 81 esd esd yes 17957 11840 171 gnd gnd yes - 17960 - 11840 82 v2_c v2 no 17957 12440 172 v2_a v2 no - 17960 - 12440 83 v2_c v2 no 17957 13040 173 v2_a v2 no - 17960 - 13040 84 v1_c v1 no 17957 13640 174 v1_a v1 no - 17960 - 13640 85 v1_c v1 no 17957 14240 175 v1_a v1 no - 17960 - 14240 86 vh_c vh no 17957 14840 176 vh_a vh no - 17960 - 14840 87 n/c - no 17957 15440 177 h1_a1 h1 yes - 17960 - 15440 88 n/c - no 17957 16040 178 h2_a1 h2 yes - 17960 - 16040 89 og_c og yes 17957 16640 179 og_a og yes - 17960 - 16640 90 rd_c rd no 17957 17240 180 rd_a rd no - 17960 - 17240 figure 12 : bond pad assignment table
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 21 d ie o rientation figure 13 : die orientation q u a d r a n t a q u a d r a n t b q u a d r a n t c q u a d r a n t d p a d 1 p a d 6 9 p a d 9 1 p a d 1 5 9 a l i g n m e n t m a r k a l i g n m e n t m a r k s i d e 1 ( v i d e o o u t p u t s 1 t h r o u g h 2 0 ) s i d e 4 - c l o c k a n d b i a s i n p u t s q u a d r a n t s a a n d d s i d e 3 ( v i d e o o u t p u t s 2 1 t h r o u g h 4 0 ) s i d e 2 - c l o c k a n d b i a s i n p u t s q u a d r a n t s b a n d c
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 22 p ad o ne m ark figure 14 : pad one marker d ie a lignment m ark figure 15 : die alignment marks the alignment marks are on a diagonal line passing through the optical and geometric center of the die . mark location x (m) y (m) top left - 18229.9 17737.2 bottom right 18229.9 - 17737.2 p a d o n e m a r k e r u p p e r l e f t m a r k l o w e r r i g h t m a r k
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 23 performance p ower C e stimated amplifier 1st & 2nd 3rd current (ma ) 0.75 5 voltage (v) 15 7 outputs 40 40 power (mw) 450 1400 parameter vccd (gnd) vccd (v1 - v2) hccd (gnd) hccd (h1 - h2) capacitance (nf) 400 24 0.8 0.2 voltage (v) 9 18 5 10 frequency (m h z) 0.071 0.071 17 17 power (mw) 2305 553 340 340 total estimated power is 5.4w. this power estimate uses a simple model of fcv 2 . this is will overestimate the power dissipated by the ccds. the output amplifier power values are expected to be accurate.
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 24 imaging performance i mage p erformance o perational c onditions unless otherwise noted, the imag ing performance specifications are measured using the following conditions: description condition notes frame time 33 msec 1 horizontal clock frequency 20 mhz light source (led) green illumination centered 530 nm 2 operation nominal operating voltages and timing notes: 1. electronic shutter is not used. integration time equals frame time. 2. leds used: blue: nichia nlpb500, green: nichia nspg500s and red: hp hlmp - 8115. i maging p erformance s pecifications description symbol min. nom. max. units sample plan test temp ( c) notes dark current <200 <500 pa/cm 2 die 20 1 maximum photoresponse nonlinearity nl 2 3 % die 20 2, 3 maximum gain difference between outputs ? g 4 10 % die 20 2, 3 horizontal ccd charge capacity hne 60 65 ke - design 20 vertical ccd charge capacity vne 54 60 ke - die 20 photodiode charge capacity pne 45 50 ke - die 20 horizontal ccd charge transfer efficiency hcte 0.99997 design 20 vertical ccd charge transfer efficiency vcte 0.99999 design 20 photoresponse non - uniformity prnu 1 - 3 % die 20 photodiode dark current ipd 60 e/p/s die 20 photodiode dark current ipd 0.05 0.2 na/cm 2 die 20 vertical ccd dark current ivd 280 e/p/s die 20 vertical ccd dark current ivd 0.2 0.5 na/cm 2 die 20 image lag lag <10 50 e - die 20 antiblooming factor xab 100 200 device 20 vertical smear smr 85 db device 20 sensor read noise ne - t 23 25 e - rms design 20 4 output amplifier dc offset vodc 4 8.5 14 v die 20 output amplifier impedance rout 100 130 200 ohms die 20 output amplifier sensitivity ? v/ ? n 30 32 - v/e - die 20 solar weighted average quantum efficiency qem in 29 31 % device 20 modulation transfer function mtf 55 58 % fm device 20 notes: 1. before irradiation. 2. value is over the range of 10% to 90% of photodiode saturation. 3. value is for the sensor operated without binning 4. the value does not directly include the system noise. the s ystem electronics noise (at 20mhz) is subtracted out in quadrature .
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 25 t ypical p erformance c urves quantum efficiency figure 16 : monochrome quantum efficiency angular quantum efficiency figure 17 : angular quantum efficiency 0 10 20 30 40 50 60 350 450 550 650 750 850 950 qe (%) wavelength (nm) goal f296z wafer 9 die 22:20 f877z wafer 12 die 21:20 0 10 20 30 40 50 60 -20 -15 -10 -5 0 5 10 15 20 qe (%) angle (degrees) horizontal angle qe 450 nm 530 nm 600 nm f877z wafer 12 die
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 26 horizontal and vertical mtf figure 18 : kai - 18000 horizontal mtf f igure 19 : kai - 18000 vertical mtf minimum horizontal mtf for 002 and p12 0.5 0.6 0.7 0.8 0.9 1 0.2 0.4 0.6 0.8 1 f/fn mtf red, 002 average red, 002-1 red, 002-2 red, 002-3 blue, 002 average blue, 002-1 blue, 002-2 blue, 002-3 red, p12 average red, p12-2 red, p12-4 blue, p12 average blue, p12-2 blue, p12-4 spec vertical mtf for 002 and p12 0.5 0.6 0.7 0.8 0.9 1 0.2 0.4 0.6 0.8 1 f/fn mtf red, 002 average red, 002-v1 red, 002-v2 red, 002-v3 blue, 002 average blue, 002-v1 blue, 002-v2 blue, 002-v3 red, p12 average red, p12-1 red, p12-2 blue, p12 average blue, p12-1 blue, p12-2 spec
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 27 defect definitions s pecifications description definition monochrome with microlens only major dark field defective bright pixel defect 25 mv 200 major bright field (80% saturation) defective dark pixel defect 15% minor dark field defective bright pixel defect 8 mv 2000 cluster defect a group of 2 to 10 contiguous major defective pixels, but no more than 2 adjacent defects horizontally 80 column defect a group of more than 10 contiguous major defective pixels along a single column 1 notes: 1. column and cluster defects are separated by no less than two (2) pixels in any direction (excluding single pixel defects).
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 28 operation m aximum r atings description symbol minimum maximum units notes temperature t - 50 50 c 1 humidity rh 5 90 % 2 output bias current iout 0.0 6.0 ma 3 off - chip load c l 25 pf 4 notes: 1. noise performance will degrade at higher temperatures. 2. t=25 c. excessive humidity will degrade mttf. 3. total for both outputs. current is 5 ma for each output. note that the current bias affects the amplifier bandwidth. 4. with the maximum clock frequency of 17 mhz. absolute maximum rating is defined as a level or condition that should not be exceeded at any time per the description . if the level or the condition is exceeded, the device will be degraded and may be damaged. m aximum v oltage r atings b etween p in ( or f unction ) description minimum maximum units notes r, vh, h1, h2, og, and gnd to esd 0 17 v pin to pin with esd protection - 17 17 v 1 vdd to gnd 0 25 v notes: 1. pin functions with esd protection are: r, vh, h1, h2, and og. e xpected r ange of dc b ias o perating c onditions description symbol minimum nominal maximum units maximum dc current (ma) notes output gate og - 3.25 - 3.0 - 2.75 v 0.001 reset drain rd 12.25 12.5 12.75 v 0.001 output amplifier supply vdd 14.5 15.0 15.5 v 0.8 3 ground gnd 0.0 0.0 0.0 v substrate sub 8.0 vab 15.0 v 1 esd protection esd - 9.5 - 9.0 - 8.5 v 1.0 2 notes: 1. the operating value of the substrate voltage, vab, will be marked on the shipping container for each device. the value vab is set such that the photodiode charge capacity is still linear; 0.5 volt away from peak value. 2. vesd must be more negative than h1, h 2, og, gnd, and r during sensors operation and during camera power turn on. 3. one output, unloaded .
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 29 ac o perating c onditions expected range of clock levels description symbol minimum nominal maximum units notes vertical ccd clock high v2h 9.75 10.0 10.25 v vertical ccd clock midlevel v1m, v2m - 0.25 0.0 0.25 v 1 vertical ccd clock low v1l, v2l - 9.25 - 9.0 - 8.75 v 2 horizontal ccd clock high h1h, h2h 0.25 0.5 0.75 v 3 horizontal ccd clock low h1l, h2l - 5.25 - 5.0 - 4.75 v horizontal ccd clock amplitude h1, h2 5 v 4 reset clock low - specified value rl - 2.9 - 2.8 - 2.7 v 6 reset clock amplitude ramp 5.5v 7 electronic shutter voltage vshutter 37 40 44 v vertical - horizontal high vhh 2 2.25 2.5 v 5 vertical - horizontal low vhl - 9.25 - 9 - 8.75 v 2 notes: 1. v1m and v2m must be the same voltage 2. v1l, v2l, and vhl must be the same voltage 3. h1h and h2h must be the same voltage 4. h1 and h2 must have the same offset and amplitude 5. for improved radiation durability set vhh 1v higher than v1m, v2m 6. the reset clock low voltage will be specified for each kai - 18000 image sensor delivered to the customer. the tolerance allowed for the actual reset clock low voltage. 7. a minimum level for t he reset clock amplitude is specified. the reset clock high level (rh) can be defined as the actual reset clock low level plus a fixed minimum amplitude (ramp). see figure 33 : reset and hccd timing detail .
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 30 power up sequence adherence to the power - up and power - down sequence is critical. failure to follow the proper power - up and power - down sequences may cause damage to the sensor. figure 20 : power up and power down se quence notes: 1. activate all other biases when esd is stable and sub is above 3v 2. do not pulse the electronic shutter until esd is stable 3. vdd cannot be +15v when sub is 0v 4. the image sensor can be protected from an accidental improper esd voltage by current l imiting the sub current to less than 10ma. sub and vdd must always be greater than gnd. esd must always be less than gnd. placing diodes between sub, vdd, esd and ground will protect the sensor from accidental overshoots of sub, vdd and esd during power on and power off. see the figure below. 5. an acceptable power - up sequence can be energize vsub followed by esd, then, when esd is stable, energize rd, vdd, og. the remaining clock levels can be activated in any order. the vccd clock waveform must not have a n egative overshoot more than 0.4v below the esd voltage. figure 21 : vccd clock negative overshoot example of external diode protection for sub, vdd and esd. denotes 1 - 40 . figure 22 : external diode protection recommendation vdd sub esd vccd low hccd low time v+ v- activate all other biases when esd is stable and sub is above 3v do not pulse the electronic shutter until esd is stable all vccd clocks absolute maximum overshoot of 0.4v 0.0v esd esd - 0.4v gnd sub vdd ? esd
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 31 clock line capacitances figure 23 : clock line capacitance all bond pads have a capacitance of 3.1pf not included in this figure. note s : 1. the clock line capacitances do not include all input impedance characteristics of the kai - 18000 device. as such, they do not fully represent a valid equivalent circuit model. the capacitance drawings are only provided to help estimate the current drive requirements on the respective v and h clocks. p e r q u a d r a n t r o w ( 2 1 6 0 p i x e l s ) p e r s e n s o r ( 1 8 . 3 m p i x e l s ) p e r q u a d r a n t ( 4 . 6 m p i x e l s ) p e r h i n p u t ( 1 0 8 0 p i x e l s ) g n d g n d g n d 5 1 p f 5 1 p f 2 5 p f 5 0 p f h 1 v h g n d g n d g n d s u b 2 0 n f 5 0 n f 5 0 n f 6 n f v 2 v 1
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 32 figure 24 : reset clock line capacitance note s : 1. the clock line capacitances do not include all input impedance characteristics of the kai - 18000 device. as such, they do not fully represent a valid equivalent circuit model. the capacitance drawings are only provided to help estimate the current drive requirements on the respective reset clocks.
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 33 figure 25 : rd and og line capacitances 3.1pf 320ff ???? 200ff 3.3 ? vout1 940ff ???? 200ff 3.3 ? vout2 940ff ???? 200ff 3.3 ? vout3 940ff ???? 200ff 3.3 ? vout4 940ff ???? 200ff 3.3 ? vout5 940ff ???? 200ff 3.3 ? vout6 940ff ???? 200ff 3.3 ? vout7 940ff ???? 200ff 3.3 ? vout8 940ff ???? 200ff 3.3 ? vout9 940ff ???? 200ff 3.3 ? vout10 rd bond pad 3.1pf 590ff ???? 200ff 3.3 ? vout1 940ff ???? 200ff 3.3 ? vout2 940ff ???? 200ff 3.3 ? vout3 940ff ???? 200ff 3.3 ? vout4 940ff ???? 200ff 3.3 ? vout5 940ff ???? 200ff 3.3 ? vout6 940ff ???? 200ff 3.3 ? vout7 940ff ???? 200ff 3.3 ? vout8 940ff ???? 200ff 3.3 ? vout9 940ff ???? 200ff 3.3 ? vout10 og bond pad 3.1pf 320ff ???? 200ff 3.3 ? vout20 940ff ???? 200ff 3.3 ? vout19 940ff ???? 200ff 3.3 ? vout18 940ff ???? 200ff 3.3 ? vout17 940ff ???? 200ff 3.3 ? vout16 940ff ???? 200ff 3.3 ? vout15 940ff ???? 200ff 3.3 ? vout14 940ff ???? 200ff 3.3 ? vout13 940ff ???? 200ff 3.3 ? vout12 940ff ???? 200ff 3.3 ? vout11 rd bond pad 3.1pf 590ff ???? 200ff 3.3 ? 940ff ???? 200ff 3.3 ? 940ff ???? 200ff 3.3 ? 940ff ???? 200ff 3.3 ? 940ff ???? 200ff 3.3 ? 940ff ???? 200ff 3.3 ? 940ff ???? 200ff 3.3 ? 940ff ???? 200ff 3.3 ? 940ff ???? 200ff 3.3 ? 940ff ???? 200ff 3.3 ? og bond pad vout20 vout19 vout18 vout17 vout16 vout15 vout14 vout13 vout12 vout11
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 34 t iming r equirements (f or 17 mh z o peration ) description symbol minimum nominal maximum units notes vccd delay tvd 2.0 s horizontal retrace time tvt 1.0 s vh transfer time high tvhm 0.25 s vh transfer time low tvhl 0.50 s vccd transfer time high tvm 3 s vccd transfer rise/fall time tvs 4.029 s line time tl 14.058 s vccd transfer rise/fall time tvs 4.029 s photodiode transfer time tv2h 10.0 s vccd pedestal time tvpd 20 s vccd delay tvst 200 s reset pulse time tr 6 8 ns reset pulse rise time trt 0 4 ns reset/hccd alignment thr 0 2 4 hccd clock level time th 21.4 hccd clock rise time tht 0 8 10 shutter pulse time tsh 5 s pixel clock period tpix 58.82353 ns
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 35 t iming image readout flow figure 26 : image readout flow the image readout sequence begins with the photodiode to vccd transfer. the transfer gate is turned on by raising the v2 gate voltage above 9 v. the integration time ends on the falling edge transition from the v2 high level to the v2 midleve l voltage. each vccd clock cycle transfers the entire image one line towards the hccd. the first 32 lines will contain only vccd dark current and smear signal. the next 2080 lines will contain data from photoactive pixels. while the vccd is emptied in 211 2 lines, 2314 lines are needed to stretch out the total frame time to 33.3 ms. the vccd should be clocked continuously. stopping the vccd clock will cause non - uniformities in dark current and smear signal. p h o t o d i o d e r e a d o u t v c c d l i n e t r a n s f e r r e a d o u t 6 d u m m y p i x e l s f r o m h c c d r e p e a t f o r 2 3 1 4 l i n e s r e a d o u t 2 1 6 i m a g e p i x e l s f r o m h c c d
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 36 electronic shutter timing flow figure 27 : electronic shutter timing flow p h o t o d i o d e r e a d o u t v c c d l i n e t r a n s f e r r e a d o u t 6 d u m m y p i x e l s f r o m h c c d r e p e a t f o r 2 3 1 4 - n l i n e s r e a d o u t 2 1 6 i m a g e p i x e l s f r o m h c c d p u l s e v s u b f o r e l e c t r o n i c s h u t t e r v c c d l i n e t r a n s f e r r e a d o u t 6 d u m m y p i x e l s f r o m h c c d r e a d o u t 2 1 6 i m a g e p i x e l s f r o m h c c d r e p e a t f o r n l i n e s
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 37 electronic shutter description the voltage on the substrate (sub) determines the charge capacity of the photodiodes. when sub is 8 volts the photodiodes will be at their maximum charge capacity. increasing vsub above 8 volts decreases the charge capacity of the photodiodes until 45 vol ts when the photodiodes have a charge capacity of zero electrons. therefore, a short pulse on sub, with a peak amplitude greater than 45 volts, empties all photodiodes and provides the electronic shuttering action. it may appear the optimal substrate volta ge setting is 8 volts to obtain the maximum charge capacity and dynamic range. while setting vsub to 8 volts will provide the maximum dynamic range, it will also provide the minimum antiblooming protection. the kai - 18000 vccd has a charge capacity of 60, 000 electrons (60 ke - ). if the sub voltage is set such that the photodiode holds more than 60 ke - , then when the charge is transferred from a full photodiode to vccd, the vccd will overflow. this overflow condition manifests itself in the image by making b right spots appear elongated in the vertical direction. the size increase of a bright spot is called blooming when the spot doubles (or more) in size. the blooming can be eliminated by increasing the voltage on sub to lower the charge capacity of the photo diode. this ensures the vccd charge capacity is greater than the photodiode capacity. there are cases where an extremely bright spot will still cause blooming in the vccd. normally, when the photodiode is full, any additional electrons generated by photons will spill out of the photodiode. the excess electrons are drained harmlessly out to the substrate. there is a maximum rate at which the electrons can be drained to the substrate. if that maximum rate is exceeded (for example, by a very bright light sourc e) . it is possible for the total amount of charge in the photodiode to exceed the vccd capacity. this results in blooming. the amount of antiblooming protection also decreases when the integration time is decreased. there is a compromise between photodiod e dynamic range (controlled by vsub) and the amount of antiblooming protection. a low vsub voltage provides the maximum dynamic range and minimum (or no) antiblooming protection. a high vsub voltage provides lower dynamic range and maximum antiblooming pro tection. the optimal setting of vsub is specified separately for each kai - 18000 image sensor. the given vsub voltage for each sensor is selected to provide antiblooming protection for bright spots at least 100 times saturation, while maintaining at least 5 0 ke - of dynamic range. the electronic shutter provides a method of precisely controlling the image exposure time without any mechanical components. if an integration time of t int is desired, then the substrate voltage of the sensor is pulsed to at least 40 volts t int seconds before the photodiode to vccd transfer pulse on v2. use of the electronic shutter does not have to wait until the previously acquired image has been completely read out of the vccd. large signal output the charge handling capacity of the output amplifier is set by the reset clock voltage levels. the reset clock driver circuit is very simple if an amplitude of 5 v is used. the low level of the reset clock determines the maximum amount of charge that can be sampled by the output amplif ier. the high level determines how stable the video dc offset level will be. the large signal output of kai - 18000 (1.5 v) requires that the low level voltage of the reset clock be fine - tuned for each kai - 18000 image sensor. this will ensure the maximum a mount of reliability from channel potential shifts caused by radiation damage.
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 38 line timing + figure 28 : line timing charge begins to transfer from the vertical to the horizontal ccd on the rising edge of the vh clock. the transf er is completed 500 ns after the falling edge of the vh clock. the h1 and h2 clocks must be stopped during the vh transfer time. the main vccd in the pixel array cannot transfer in 1 s so the v1 and v2 clock transitions are spread out over the entire 14.0 58 s line time. the v1 and v2 clocks have a large capacitive coupling to the gnd (p - well) of the image sensor. any rapid changes or glitches on the v1 or v2 clocks will likely couple into the video output and degrade image quality. image artifacts are be st avoided by ensuring a smooth, and as slow as possible clock waveform that will fit into 14.058 s. the line timing should be repeated continuously even after the last photoactive line has been read out. this will ensure a uniform dark current and smear signal background level. the only exception is when the sensor is in stand - by mode. in standby mode the v1, v2, vh, h1, and h2 clocks are set at 0 v. at the end of standby mode clock the vccd for at least 100 ms before acquiring the first image. figure 29 : line timing detail vh v2 v1 h1 h2 t vt t vhl t vm t vs t l round corners for reduced image artifacts 17.00 mhz hccd 6 dummy pixels followed by 216 active pixels v1l v1m v2l v2m vhl vhh h2l h2h h2l h2h t vd t vhm t vm t vs t vm 222 1 2 3 4 5 6 7 8 222 221 pixel video h2 h1 17 clock cycles 6 clock cycles 216 clock cycles 1 line = 239 clock cycles = 14.05882 s
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 39 edge alignment v1 and v2 clock figure 30 : example of vertical clock crossover - targeted at 50% notes: 1. trace 1: v1 clock 2. trace 2: v2 clock for good video waveforms the circuit design should target a v1 - v2 crossover at 50% .
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 40 frame timing figure 31 : frame timing the frame timing sequence causes all photodiodes to transfer their charge to the vccd. the transfer completes on the falling edge of v2 from v2h to v2m. the v2 clock must be at the v2h level for at least tv2h time. the sloped edges are not critical in the frame timing because valid image data is not being sampled. the v2m to v2h rising and falling edges must be compensated by equal slopes on the v1 clock transitioning between v1m and v1l. failure to compensate those edges will result in incomplete photodiode to vccd charge transfer. t v 2 h t v s t t v s t t v p d s a m e s l o p e a s t h e l i n e t i m i n g t l v h v 2 v 1 h 1 v 2 l v 2 m v 1 l v 1 m v h l v h h h 1 l h 1 h v 2 h e x p o s u r e e n d t l
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 41 pixel timing figure 32 : pixel timing the reset clock should be coincident wit h the rising edge of the h2 clock. there is no minimum time for the rise and fall times of the clocks. the maximum rise and fall times are determined by how much time the correlated double sampling circuit needs for its sampling operations. video h2 reset t pix t r t pix 2 video reference video signal
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 42 note: r l is assigned at delivery. r h , as shown , is the peak value for this signal and is defined as r l + r amp figure 33 : reset and hccd timing detail r h r h - 0.2 r l r l + 0.2 t r t rt t rt t h t ht t ht t hr h l h l + 0.2 h h h h + 0.2 h l h l + 0.2 h h h h + 0.2
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 43 figure 34 : reset clock waveform
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 44 figure 35 : electronic shutter timing all charge in the photodiodes is discharged to the substrate when the substrate connection is pulsed above 40 v. the photodiode begin collecting photo - signal (exposure start) on the falling edge of the substrate pulse. the substrate pulse should come after the last valid pixel of a line has been read out and sampled from the hccd. hold the vccd clocks idle during the substrate pulse period. do not pulse the substrate while reading out valid image data fr om the hccd. continue clocking the reset clock and hccd during the electronic shuttering. vh v2 v1 h1 t l t sh substrate vhl vhh h1l h1h v1l v1m v2l v2m vsub vshutter exposure start t l t l t l
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 45 video loading figure 36 : video output waveform notes: 3. trace 1: video kai - 18000 waveform 4. trace 2: h clock 5. trace 3: h clock for good v ideo waveforms the total load on the image sensor video output bond pad should be less than 30 pf for a 17 mhz pixel clock. this is with a 5 ma load current on the output amplifier bond pad.
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 46 noise factors the following list ranks the input pins of the ima ge sensor in order of their importance to noise performance. 1. og 2. reset (clock level and timing jitter) 3. gnd 4. vdd 5. h2 (timing jitter) 6. h1 (timing jitter) 7. rd 8. v1, v2, vh 9. sub 10. esd og and reset will couple noise onto the output with about a 5 to 1 ratio. a 5 v change on og or reset will produce approximately a 1 v change on the output. for h1 and h2 timing stability is more important than clock level stability.
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 47 storage and handling s torage c onditions description symbol minimum maximu m units notes storage temperature t st - 55 50 c 1 humidity rh 5 90 % 2 notes: long - term storage toward the maximum temperature will accelerate color filter degradation. t = 25 c. excessive humidity will degrade mttf. esd 1. this device contains limited protection against electrostatic discharge (esd). esd events may cause irreparable damage to a ccd image sensor either immediately or well after the esd event occurred. failure to protect the sensor from electrostatic discharge may affect device performance and reliability. 2. devices should be handled in accordance with strict esd procedures for class 0 (<250 v per jesd22 human body model test), or class a (<200 v jesd22 machine model test) devices. devices are shipped in static - safe containers and should only be handled at static - safe workstations. 3. see application note image sensor handling best practices for proper handling and grounding procedures. this application note also contains workplace recommendations to minimize elect rostatic discharge. 4. store devices in containers made of electro - conductive materials. c over g lass c are and c leanliness 1. the cover glass is highly susceptible to particles and other contamination. perform all assembly operations in a clean environment. 2. t ouching the cover glass must be avoided. 3. improper cleaning of the cover glass may damage these devices. refer to application note image sensor handling best practices . e nvironmental e xposure 1. extremely bright light can potentially harm ccd image sensors. do not expose to strong sun light for long periods of time, as the color filters and/or microlenses may become discolored. in addition, long time exposures to a static high contrast scene should be avoided. localized changes in response may occur from color filter/microlens aging. for interline devices, r efer to application note using interline ccd image sensors in high intensity visible lighting conditions. 2. exposure to temperatures exceeding maximum specified levels should be avoided for storage and operati on, as device performance and reliability may be affected. 3. avoid sudden temperature changes. 4. exposure to excessive humidity may affect device characteristics and may alter device performance and reliability, and therefore should be avoided. 5. avoid storage of the product in the presence of dust or corrosive agents or gases. long term storage (>1 year) should be avoided.
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 48 mechanical drawings c ompleted a ssembly figure 37 : completed assembly
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 49 f igure 38 : glass drawing
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 50 quality assurance and reliability q uality and r eliability all image sensors conform to the specifications stated in this document. this is accomplished through a combination of statistical process control and visual inspection and electrical testing at key points of the manufacturing process, using industry standard methods. information concerning the quality assurance and reliability testing procedures and results are available from on semiconductor upon request. for further information refer to applicatio n note quality and reliability . r eplacement all devices are warranted against failure in accordance with the terms of sale . devices that fail due to mechanical and electrical damage caused by the customer will not be replaced. l iability of the s upplier a reject is defined as an image sensor that does not meet all of the specifications in this document upon receipt by the customer. pr oduct liability is limited to the cost of the defective item, as defined in the terms of sale . l iability of the c ustomer damage from mishandling (scratches or breakage), electrostatic discharge (esd), or other electrical misuse of the device beyond the stated operating or storage limits, which occurred after receipt of the sensor by the customer, shall be the responsibility of the customer. t est d ata r etention image sensors shall have an identifying number traceable to a test data file. test data shall be kept for a period of 2 years after date of delivery. m echanical the device assembly drawing is provided as a reference. on semiconductor reserves the right to change any information c ontained herein without notice. all information furnished by on semiconductor is believed to be accurate. life support applications policy on semiconductor image sensors are not authorized f or and should not be used within life support systems without the specific written consent of on semiconductor .
ka i - 18000 image sensor www.truese nseimaging.com revision 3.1 ps 0067 pg 51 ? 2014, semiconductor components industries, llc. revision changes mtd/ps - 1416 revision number description of changes 1.0 ? formal reissue (previous format version was label e d as revision 2.0) . 3.0 ? resequence the revision to match historical releases. ? this revision release had an update to the esd circuit and the power up sequence. ? a defect specification section is included. ? change to applications use on front page. ? rename part number for pr oprietary package type in ordering information section. ? maximum ratings table added 3.0_2 ? updated corrections and formatting in summary specification; title, size of imager, etc. ? removal of iss references throughout ? updated miscellaneous formatting items. ? updated contact information under ordering information section. ? updated pixel array layout description in device description - architecture section ? corrected reference to esd pin descriptions as contained in bond pad assignment table ? removal of clas s reference in defect definitions table. ? updating company referenced in life support applications policy and specification liability statement. ps 0067 revision number date description of changes 1 .0 9/21/12 ? initial release with new document number, updated branding and document template ? updated storage and handling and quality assurance and reliability sections ? updated limits for output amplifier, qe, mtf, and total read noise ? added microlens to the description of the 4h0402 version in ordering infor mation. ? revised definition of reset clock waveform. components specified are reset clock low level and reset clock amplitude. ? added a clock signal waveform, see figure 34 : reset clock waveform . ? corrected the ordering information section to reflect four part number version. ? left vr line items in specification parameter table to be tbd (to be reviewed) ? sensor read noise entry created. replaces read noise. ? removed marking code on ordering information ? added a scope trace to show 50% crossover example of the vertical clock. 2 .0 10/ 1/12 ? correction to ordering information C part names. 3 .0 5 / 3 0/13 ? update to final tbr values associated with reset clock swing level . remove the requirement for vh to be managed as other pins for esd protection (that is not applicable to vh). 3.1 6/4/14 ? updated branding

▲Up To Search▲

Price & Availability of 4H2259

	To Download 4H2259 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .